1. Field of the Invention
This invention generally relates to testing of semiconductor device packages and, more particularly, to a method for defect testing of an integrated circuit from the back side.
2. Description of the Related Art
During integrated circuit manufacturing, a large number of identical integrated circuit devices (e.g., a microprocessor) are typically produced upon a unitary silicon substrate in an array of rectangular elements called xe2x80x9cdicexe2x80x9d. Signal lines which are formed upon the silicon substrate for each individual device are terminated at flat metal contact regions called input/output (I/O) pads. The signal lines are to be connected to external devices. Following manufacture, the substrate is sliced into individual dice or chips, and each chip is secured within a protective semiconductor device package. The role of the package is to provide mechanical support, electrical connection, protection, and heat removal for the die. Each I/O pad of the chip is connected to one or more terminals of the device package. The terminals of a device package are typically arranged about the periphery of the package. Fine metal wires may be used to connect the I/O pads of the chip to the terminals of the device package. Some types of device packages have terminals called xe2x80x9cpinsxe2x80x9d for insertion into holes in a printed circuit board (PCB). Other types of device packages have terminals called xe2x80x9cleadsxe2x80x9d for attachment to flat metal contact regions on an exposed surface of a PCB.
The controlled collapse chip connection (xe2x80x9cC4xe2x80x9d) is a well known method of attaching an integrated circuit chip directly to a PCB, and is commonly referred to as the xe2x80x9cflip chipxe2x80x9d method. In preparation for C4 attachment, the I/O pads of the chip are arranged in a two-dimensional array upon a top side of the chip, and a corresponding set of bonding pads are formed upon an upper surface of the PCB. A solder ball (or bump) is formed upon each of the I/O pads of the chip. During C4 attachment of the chip to the PCB, the solder balls are placed in physical contact with the bonding pads of the PCB. To accomplish this the chip is xe2x80x9cflippedxe2x80x9d so that the top side of the chip is facing down toward the PCB while the back side of the chip is facing up. The solder balls are then heated long enough for the solder to flow. When the solder cools, the I/O pads of the chip are electrically and mechanically coupled to the bonding pads of the PCB. After the chip is attached to the PCB, the region between the chip and the PCB is filled with an xe2x80x9cunderfillxe2x80x9d material which encapsulates the C4 connections and provides other mechanical advantages.
A ball grid array (xe2x80x9cBGAxe2x80x9d) device package includes a chip mounted upon a larger substrate made of, for example, fiberglass-epoxy printed circuit board material or a ceramic material (e.g., aluminum oxide, alumina, or aluminum nitride). FIG. 1 depicts a an exemplary BGA device package 10. The substrate 14 includes two sets of bonding pads: a first bonding pad set 16 adjacent to the chip 12 and a second bonding pad set 18 arranged in a two-dimensional array across the underside surface of the device package 10. The I/O pads 20 of the chip 12 are typically connected to corresponding members of the first bonding pad set 16 via solder bumps 22 using the C4 technique described above. One or more layers of signal lines (i.e., interconnects) of the substrate 14 connect respective members of the first and second sets of bonding pads. Members of the second bonding pad set 18 are coated with solder, forming solder ball terminals 24. A stiffener 26 may be attached to the perimeter of the upper surface of substrate 14 by a first adhesive layer 28. Stiffener 26 may help to maintain the substantially planar shape of substrate 14 during and after C4 heating of solder bumps 22.
A heat spreader 30 may also be attached to the upper surface of substrate 14 by a second adhesive layer 32 and a thermally conductive layer 34 interposed between chip 12 and heat spreader 30. Heat spreader 30 may be composed of copper which exhibits high thermal conductivity. During operation, semiconductor devices (e.g., integrated circuit chips) dissipate electrical power, transforming electrical energy into heat energy. Heat spreader 30 permits the heat energy produced by chip 12 to be removed to the ambient environment at a rate which ensures operational and reliability requirements are met. Without this heat transfer, the temperature of chip 12 might exceed a specified operating temperature, resulting in irreversible damage to the chip.
After a chip is packaged, it may undergo testing to identify any device damage that may have occurred during the assembly of the package. Moreover, certain elements of device performance, such as speed, can only be measured in the completed package. For some devices, final testing may be preceded by a xe2x80x9cburn-inxe2x80x9d in which the device is operated for a period of time under stress. Such devices are then tested to determine if performance of the devices is still acceptable. Various types of failure mechanisms can occur. For example, the chip passivation layer which is usually made of brittle glass films may crack. Metallization on the chip may deform as a result of shear stresses between the package elements and the chip. Voids and cracks may also occur in the package itself. Adhesive layers between the chip and the package may undergo delamination.
Various types of tests are used to perform failure analysis of a chip and its package. For example, infrared absorption spectroscopy and emission spectroscopy may be used to analyze the top surface of the chip for fault localization. Acoustic microscopy may be used to determine if any delaminations or voids exist in e.g., adhesion layers of the package. Before performing failure analysis of a chip and its package, access to the chip and the inside of the package must be obtained for most conventional testing techniques to be applied. Conventional techniques for gaining access to a chip packaged according to FIG. 1 involve removal of the stiffener from the substrate. Separating the stiffener 26 from substrate 14, so as to gain access to integrated circuit 12 and substrate 14, often results in damage to substrate 14.
Most chips prepared for use in flip-chip packages include a metal layer extending across the top side of the chip. In addition, a number of bumps are arrayed across the top of the chip for connecting to the package. These layers make it difficult to analyze the underlying integrated circuits using a top side analysis. Furthermore, even on non-flip chip dies, the current use of 5 to 7 interconnect layers makes the inspection and failure analysis very difficult.
It would be beneficial to have a method that allows testing of a chip packaged using a flip chip integrated circuit package without having to remove the chip from the package. Such a method would facilitate subsequent chip examination for failure analysis after a chip has been packaged.
The problems outlined above are in large part solved by the technique hereof for testing the backside of an integrated circuit chip. By testing the backside of an integrated circuit, the chip may remain partially enclosed by a package while testing is being performed. This is especially useful for flip chip packaging arrangements.
The method uses liquid crystal microscopy to analyze the back side of an integrated circuit chip for the location of defective components of the chip. Typically, the chip may be enclosed in a package. Prior to testing, the package may be partially disassembled to expose the back surface of the chip. Alternatively, the chip may not be packaged at all, thus the back surface is immediately accessible. In another embodiment, the chip may be fully package, however, the package design may be such that the backside of the chip is normally exposed.
Once the chip is exposed, a thin film of a liquid crystal material is applied to the back side of the chip. Two types of liquid crystals are commonly used for failure analysis of semiconductor devices, cholesteric liquid crystals and nematic liquid crystals. Cholesteric liquid crystals typically exhibit color changes in response to temperature differences on the chip. Defects within the chip may cause hot or cold regions on the chip, when compared to a properly functioning chip. These hot or cold regions may be apparent when viewing the temperature sensitive liquid crystal. Nematic liquid crystals typically exhibit color changes in response to localized changes in the electric field. When a properly working chip is covered with a nematic liquid crystal, a pattern may be formed corresponding to the electric fields produced by the electrical components within the chip. If a portion of the chip includes defects, the localized electric field may be altered in the vicinity of the defect, causing a change in the visual appearance of the liquid crystal.
In one embodiment, the backside of the chip may be polished to enable localization of the failure site. Since the backside of the chip is typically composed of single crystal silicon, an infrared analysis may be used to visualize the location of the individual integrated circuits. Single crystal silicon substrates are substantially transparent to infrared radiation. However, during the processing of the chip, the backside may be roughened and scratched such that the visualization of the integrated circuits would be difficult. By polishing the backside of the chip, IR and other tests may be performed to help locate the site of the defect.
After applying the liquid crystal to the back side of the chip, a voltage is applied to the chip and a series of tests designed to test many of the individual components of the chip may be run. During these tests the chip is placed in an electrical failing mode for analysis. This may be accomplished by powering up the chip. Alternatively, the chip may be placed in a variety of electrical modes to determine the presence and type of defect. The chip may be placed in a socket that includes a number of contact points configured to mate with corresponding pads coupled to the chip. The pads may be formed upon the top surface of the chip, allowing backside analysis of an unpackaged chip. In another embodiment, a partially packaged chip may be placed in a socket configured to apply a voltage to the chip. The partially packaged chip may include a number of conductive pads, arranged on the bottom of the package, and coupled to the contact pads on the top surface of the chip. The conductive pads may make contact with conductive features in the socket. A voltage may therefore be applied to the chip via the conductive pads on the bottom of the package.
As a voltage is applied to the chip, the liquid crystal on the backside of the chip is optically inspected to determine if any defects are present. As mentioned above, defects that cause temperature differences or electric field differences in the chip may induce a visual change in the appearence of the liquid crystal layer. In one embodiment, an optical microscope may be used to inspect the liquid crystal layer. The optical microscope may include a pair of polarizing filters. A first polarizing filter may be placed in front of the light source such that polarized light strikes the liquid crystal during the optical inspection. A second polarizing filter may be placed in front of the light receiving element to allow the detection of changes in the angle of polarization of the light.